Formation

– Doctorat en microélectronique à l’INPG (Institut National Polytechnique de Grenoble),
Laboratoire d’accueil TIMA, groupe SLS. Thèse sujet «Spécification et validation des systèmes hétérogènes embarqués» (1999-2002)
– Ms.S. (Equivalence DEA Microélectronique) à l’Université Polytechnique de Bucarest, Faculté d’Electronique et de Télécommunications. Spécialité : Fiabilité et Qualité des Systèmes Microélectroniques, mention très bien (major) (1998-1999)
– Diplôme d’Ingénieur à l’Université Polytechnique de Bucarest, Faculté d’Electronique et de Télécommunications, mention très bien (1993-1998)

Expérience Professionnelle

08/2003 – présent:
Professeur adjoint à l’École Polytechnique de Montréal, département Génie Informatique
Enseignement des courses: Architecture des Ordinateurs, Systèmes Temps-Réel, Systèmes embarqués

04/2003 – 08/2003:
Postdoc, Université de Montréal. Bourse de l’OTAN à incidence industrielle

04/2002 – 04/2003:
ATER (Attaché Temporaire dans l’enseignement et la Recherche ), Université Joseph Fourier – Enseignement de travaux dirigés «Recherche Opérationnelle»

1999-2002:
Doctorant au laboratoire TIMA (Techniques of Informatics and Microelectronics for computer Architecture) réunissant, dans le groupe SLS (System Level Synthesis)

2001-2002:
ENSERG (Ecole Nationale Supérieure d’Electronique et Radiocommunication Grenoble) – Enseignement de travaux pratiques «Méthodologies de conception de systèmes sur puce»
UJF (Université Joseph Fourier) – Enseignement du cours et des travaux pratiques «Langages de description et méthodes de conception des systèmes embarqués»

2000-2001:
UJF (Université Joseph Fourier) – Enseignement du cours et des travaux pratiques «Méthodes informatiques pour les disciplines scientifiques»
ENSIMAG (Ecole Nationale d’Informatique et de Mathématiques Appliqués de Grenoble) – Enseignement de travaux dirigées «Architecture des ordinateurs»

1999-2000:
UJF (Université Joseph Fourier) – Enseignement de travaux dirigées «Analyse Syntaxique»
ENSIMAG (Ecole Nationale Supérieure d’Informatique et de Mathématiques Appliqués de Grenoble) – Enseignement de travaux dirigées «Architecture des ordinateurs»

Liste de Publications

Publications dans des journaux
[1] W. Cesario, Y. Paviot, L. Gauthier, D. Lyonnard, G. Nicolescu, S. Yoo, A.A. Jerraya, “Object-based Hardware/Software Component Interconnection Model for Interface Design in System-on-a-chip Circuits”, Journal of Systems and Software, Elsevier Science, 2004
[2] G. Nicolescu, K. Svarstad, W. Cesario, L. Gauthier, D. Lyonnard, S. Yoo, P. Coste, A.A. Jerraya, “Desiderata for specification and design of electronic systems”, International Review Techniques et Sciences Informatiques, vol. 21, no. 3/2002, pp. 291-315
[3] A.A. Jerraya, A. Baghdadi, W.O. Cesario, L. Gauthier, D. Lyonnard, G. Nicolescu, Y. Paviot, S. Yoo, “Application-specific multiprocessor Systems-on-Chip”, Microelectronics Journal 33, Elsevier Science Ltd., 2002
[4] W. Cesario, D. Lyonnard, G. Nicolescu, Y. Paviot, S. Yoo, A.A. Jerraya, L. Gauthier M. Diaz-Nava, “Multiprocessor System-on-chip Platforms: a Component-Based Design Approach”, IEEE Design&Test of computers, Oct/Nov 2002
[5] W. Cesario, G. Nicolescu, L. Gauthier, D. Lyonnard, A.A. Jerraya, “Colif: A Design Representation for Application-Specific Multiprocessor SOCs”, IEEE Design & Test of Computers, Vol. 18 no. 5, Sept/Oct 2001, pp. 8-20
[6] F. Hessel, P. Coste, Ph. Le Marrec, N-E. Zergainoh, G. Nicolescu, J.M. Daveau, A.A. Jerraya, “Interlanguage Communication Synthesis for Heterogeneous Specifications”, Design Automation for Embedded Systems Journal, Vol.5, No.3/4, Kluwer Academic Publishers, August 2000, pp. 223-236

Livres
[7] A.A. Jerraya, G. Nicolescu, “Specification and Validation of System on Chip”, Hermes Sciences Paris, Mars 2004
[8] G. Bois, G. Nicolescu, E. M. Aboulhamid, “System-level exploration platforms for System on Chip”, Kluwer Academic Publishers, accepté pour publication en 2003

Chapitres de Livre
[9] S. Yoo, G. Nicolescu, I. Bacivarov, W. Youssef, A. Bouchhima, A.A. Jerraya, “Multi-Level Software Validation for NoC”, Chapter 10 in Networks on Chip, Kluwer Academic Publishers, 2003
[10] P. G. Paulin, C. Pilkington, M. Langevin, E. Bensoudane, K. Szabo, D. Lyonnard, G. Nicolescu, “A Multi-Processor SoC Platform and Tools for Communications Applications”, Embedded Systems Handbook, CRC Press, Florida, Editor: R. Zurawski, to appear in 2004

Conferences Internationales avec Actes et Commité de Sélection
[11] P. Paulin, C. Pilkington, M. Langevain, E. Bensoudane, G. Nicolescu, “Parallel Programming Models for a Multi-Processor SoC Platform Applied to High-Speed Traffic Management”, accepted for publication to ISSS/CODES2004 (best paper award)
[12] J. Lapalme, E.M. Aboulhamid, G. Nicolescu, L. Charest, F. Boyer, J.P. David, G. Bois, “.Net Framework – a solution for next generation tools for system level design”, IEEE DATE 2004, pp. 732-733
[13] J. Lapalme, E. M. Aboulhamid, G. Nicolescu, L. Charest, J.-P. David, F. Boyer, G. Bois, “ESys.NET: A New Solution for Embedded Systems Modeling and Simulation”, ACM SIGPLAN/SIGBED 2004 Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES’04), Washington, DC, June pp. 11-13, 2004
[14] F. Boyer, Y. Liping, E.M. Aboulhamid, L. Charest, and G. Nicolescu, “Multiple Simplescalar Processors with Introspection under SystemC”, 46 IEEE Midwest Symposium on Circuits and Systems, Cairo, Egypt, Dec., 2003, pp. 5
[15] G. Nicolescu, S.Yoo, A. Bouchhima, A.A. Jerraya, “Validation in a Component-Based Design Flow for Multicore SoCs”, ISSS’02, October 2-4, Kyoto, Japan.
[16] W. Cesario, A. Baghdadi, L. Gauthier, D. Lyonnard, G. Nicolescu, Y. Paviot, S. Yoo, A.A. Jerraya, M. Diaz-Nava, “Component-Based Design Approach for Multicore SoCs”, Proc. of DAC’02, June 10-14 2002, New Orleans, USA, pp. 287-294
[17] L. Kriaa, W. Youssef, G. Nicolescu, S. Martinez, S. Levitan, J. Martinez, T. Kurzweg, A.A. Jerraya, B. Courtois, “SystemC-Based Cosimulation for Global Validation of MOEMS”, Proc. of DTIP2002, 5-8 May 2002, Cannes-Mandelieu, France, pp. 64-70
[18] W. Cesario, Y. Paviot, A. Baghdadi, L. Gauthier, D. Lyonnard, G. Nicolescu, S. Yoo, A.A. Jerraya, M. Diaz-Nava, “HW/SW Interfaces Design of a VDSL Modem using Automatic Refinement of a Virtual Architecture Specification into a Multiprocessor SoC: a Case Study”, IEEE DATE 2002 Designers Forum, Paris, France, March 2002, pp. 165-169
[19] S. Yoo, G. Nicolescu, L. Gauthier, A.A. Jerraya, “Automatic Generation Including Fast Timed Simulation Models of Operating Systems in Multiprocessor SoC Communication Design”, IEEE DATE 2002, Paris, France, March 2002, pp. 64-70, (nominated for best paper award)
[20] G. Nicolescu, S. Martinez, L. Kriaa, W. Youssef, S. Yoo, B. Charlot, A.A. Jerraya, “Application of Multi-domain and Multi-language Cosimulation to an Optical MEM Switch Design”, IEEE ASP-DAC 2002, Bangalore, India, January 2002, pp. 426-432
[21] P. Gerin, S. Yoo, G. Nicolescu, A. A. Jerraya, “Scalable and Flexible Cosimulation of SoC Designs with Heterogeneous Multi-Processor Target Architectures”, IEEE ASP-DAC 2001, Jan. 2001, Yokohama, Japan, pp. 63-68
[22] K. Svarstad, N. Ben Fredj, G. Nicolescu, A. A. Jerraya, “A Higher Level System Communication for Object Oriented Specification and Design of Embedded Systems”, IEEE ASP-DAC 2001, Jan. 2001, Yokohama, Japan, pp. 69-77
[23] G. Nicolescu, S. Yoo, A.A. Jerraya, “Mixed-Level Cosimulation for Fine Gradual Refinement of Communication in SoC Design”, Proc. of DATE 2001, March 2001, Munich, Germany, pp. 754-759
[24] K. Svarstad, G. Nicolescu, A. A. Jerraya, “A Model for Describing Communication between Aggregate Objects in the Specification and Design of Embedded Systems”, IEEE DATE 2001, March 2001, Munich, Germany, pp. 77-84
[25] S. Yoo, G. Nicolescu, D. Lyonnard, A. Baghdadi, A. A. Jerraya, “A Generic Wrapper Architecture for Multi-Processor SoC Cosimulation and Design”, CODES 2001, Copenhague, Danemark, April 2001, pp. 201-206
[26] W. Cesario, G.Nicolescu, L. Gauthier, D. Lyonnard and A.A. Jerraya, “Colif: a Multilevel Design Representation for Application-Specific Multiprocessor System-on-Chip Design”, 12th IEEE International Workshop on Rapid System Prototyping, California, USA, June 2001, pp. 110-116
[27] Z. Juneidi, Torki K., S. Martinez, G. Nicolescu, B. Courtois, A. Jerraya, “Global Modeling and Simulation of System-on-Chip Embedding MEMS Devices”, 4th International Conference on ASIC, Proc. of ASICON 2001, Beijing, China, October 23-25, 2001, pp. 666-669
[28] A.A. Jerraya, A. Baghdadi, W. Cesario, L. Gauthier, D. Lyonnard, G. Nicolescu, Y. Paviot, S. Yoo, Invited Paper “Application-Specific Multiprocessor Systems-on-Chip”, Proc. of The Tenth Workshop on Synthesis And System Integration of Mixed Technologies (SASIMI) 2001, Nara, Japan, October 18-19 2001, pp. 317-324
[29] S. Yoo, G. Nicolescu, L. Gauthier, A.A. Jerraya, “Fast Timed Cosimulation of HW/SW Implementation of Embedded Multiprocessor SoC Communication”, HLDVT 2001, Monterey, USA, Oct. 2001, pp. 79-82
[30] G. Nicolescu, P. Coste, F. Hessel, Ph. Le Marrec, A. A. Jerraya, “Multilanguage Design of a Robot Arm Controller: Case Study”, IEEE Computer Society Workshop on VLSI 2000, Orlando, USA, April 27-28, 2000, pp. 29-34
[31] S. Mir, B. Charlot, G. Nicolescu, P. Coste, F. Parrain, N-E. Zergainoh, B. Courtois, A.A. Jerraya, M. Rencz, “Towards Design And Validation Of Mixed-Technology SOCs”, 10th ACM Great Lakes Symposium on VLSI, Chicago, USA, March 2000, pp. 9-20
[32] F. Hessel, P. Coste, G. Nicolescu, P. Le Marrec, N-E. Zergainoh, A.A. Jerraya, “Multi-level Communication Synthesis of Heterogeneous Multilanguage Specifications”, Proc. of ICCD 2000, Texas, USA, September 2000, pp. 525-530
[33] W.O. Cesario, L. Gauthier, D. Lyonnard, G. Nicolescu, A.A. Jerraya, “An XML-based Meta-model for the Design of Multiprocessor Embedded Systems”, VHDL International User’s Forum (VIUF) Fall Workshop, Orlando, FL, October 2000, pp. 75-81